The present inventions are related to systems and methods for controlling power dissipation in a semiconductor device, and more particularly to systems and methods for governing power state transition in a semiconductor device.
Modern semiconductor devices employ a variety of techniques for reducing power consumption. For example, where a portion of a design is not utilized, dynamic power dissipation may be reduced by limiting the amount of switching occurring in the transistors of the design. As dynamic power consumption has traditionally represented a significant portion of power consumed by a semiconductor device, such an approach has provided reasonable control over unnecessary power consumption. As semiconductor technologies have continued to advance, static power consumption due to leakage currents has become an increasing percentage of overall power consumption. To deal with this, additional methods for limiting power consumption in unused portions of a design have been developed. For example, power islands have been utilized that allow for all power to be switched off or otherwise adjusted to particular regions of the semiconductor device.
The aforementioned approaches for power management, while generally effective, can be problematic. For example, in a typical scenario, a portion of a design that was previously powered down through use of one or both of the aforementioned processes may be called for a subsequent operation. In such a case, power is reapplied and/or clocks are restarted to the portion of the design as it is awoken in preparation for performing a desired function. This power on process can result in an inrush current that may damage portions of the design and/or cause a temporary circuit instability.
FIG. 1 shows an example of a potentially damaging inrush current 170. During an initial steady state operational period 105, current at a level 140 is consumed. At a point, power to the circuit is reduced for operation during a low power operational period 110. During low power operational period 110, current at a relatively low level 160 is consumed. Once the circuit is again needed, current is increased to the circuit during a transient operational period 115. During transient operational period 115, current to the circuit increases from level 160 to level 150. As an artifact of the quickly transitioning current, an overshoot 180 occurs taking the current to a level substantially above level 150. Eventually, the level returns to level 150 associated with steady state operational period 120. Even though the current eventually stabilizes at a desired level, inrush current 170 can result in damage to the semiconductor device and/or a power regulator associated with the design. Such an inrush current must be accounted for in the design margin. This is an addition to the current budget/margin that produces no computational value and may add to package cost through the bloating of design margin. To reduce inrush current 170 and overshoot 180, a large capacitive load or another damping filter may be used in the design. Such an approach works reasonably well for reducing damage, but adds cost to what in many cases are very cost sensitive designs.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for providing power management in a semiconductor device.